The present disclosure relates to a circuit design generator, and in particular to systems and methods for designing reconfigurable integrated circuits.
The hardware industry has traditionally relied on Moore's law, the observation that the number of transistors on integrated circuits doubles approximately every two years, to pack more features in computing platforms every year. Each new generation of lithography has allowed more hardware to be fitted in a given die size (and therefore price point).
Fixed hardware solutions offer the best performance and lowest power consumption. However as we approach the end of Moore's law, we are beginning to see a slow-down in the shrinking of hardware from one generation to the next. This makes it desirable to share the same hardware for multiple tasks, and this has been a primary driver of reconfigurable hardware.
Various reconfigurable architectures have been proposed. There are also moves towards coarse-grained architectures in field-programmable gate arrays (FPGAs) and other reconfigurable designs in order to increase power efficiency and suitability for the mobile markets.
These designs may have heterogeneous cells but a common feature is a fixed homogenous interconnect system that is independent of the target applications. Although this enables the design to run a wide variety of applications, they also provide flexibility beyond what is needed if they are to be used for a specific family of applications. This increased flexibility comes at the cost of a circuit that is larger than necessary and an interconnect structure that is slower and more power-consuming than necessary.
Existing reconfigurable architectures are optimised manually to suit a family of applications, and this optimisation is typically only restricted to cell/node types, counts and their positions.